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Increase In Harmonics Due To Pf Capacitor Though Series Reactors Used


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#1 deep

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Posted 04 February 2010 - 03:54 PM

I am having a problem with PF capacitors.
They suppose not to increase the load harmonics as due care is taken in reactors(7%,0.6% etc) but still I found that it increases the 3 rd and 5th harmonics and above that others are eliminated.As per design 5th also need to minimize but not happening actually.
Why capacitors increases the harmonics?
Does it affects to my thyristorized switching?

Regards,
Deep

#2 marke

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Posted 04 February 2010 - 10:02 PM

Hello deep

Welcome to the forum.

I am not sure what you mean when you say that the addition of the capacitors increases the harmonics.

If you have a non linear load such as a rectifier, and you add power factor correction capacitors, then the harmonic current flowing between the non linear load and the power factor capacitors will increase due to the low impedance offered by the capacitors. The addition of the detuning capacitors will increase the impedance as the frequency increases, but the effect at 3rd harmonic is very small.

If you measure the harmonic current coming from the supply, this should not increase with the addition of the power factor capacitors. I would expect to see it reduce a little due to a limited filtering affect.

Best regards,
Mark.

#3 deep

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Posted 05 February 2010 - 06:11 AM

hi Mark,thanks for reply,

I am testing 9 KVAr bank on a pure inductive load with PF 0.85(plus some resistive heaters. load current 30Amp in each phase).

At input side of the load, I measured the harmonics and they are very low (max 1%- 5th harmonics)
But after switching my 9 kvar capacitor without reactors in either contactor switching type or thyristor switching type I found that line side harmonics increases (3,5 and 7 with 3% to 4%).
If I put 7% reactor for 9 KVAR, my aim is to reduce the harmonics generated by capacitors(from 5 and above),it works from 7th harmonics and above but 3rd & 5th now get increases due to reactor.(5%-6%).It is clear that capacitors increases the load harmonics,and at capacitor terminals measured harmonics are much more.I am thinking to adjust detune reactor freq.to less than 150Hz from current 187 Hz.Will it a good solution? The cost will increase but any how I have to get rid from these harmonics generated or amplified by capacitors itself which affecting the switching devises(SSRs).Is there any different solution for the problem.
PS - All these testings are for saving the SSR switches.We analyze that harmonics inside CAP.Panel are more,SSR failures are more.

#4 marke

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Posted 05 February 2010 - 09:53 AM

Hello deep

If you have harmonic voltages present on the supply, then there will be harmonic currents in the capacitors.
As the frequency increases, the impedance of the capacitors reduces, causing an increasing harmonic current.
The harmonics are not caused by the capacitors, rather the harmonics are caused by a distorted voltage waveform.

The only way to eliminate the harmonic currents, is to eliminate the voltage distortion on the supply.
The addition of detuning reactors will reduce the upper order harmonic currents, but will not eliminate them.

If the harmonic currents are high enough to damage/destroy the switching devices, then either the switching devices are seriously undersized, or the current will be bad enough to damage the capacitors.
If the switching devices are not correctly controlled, they can cause very high switching currents that can damage the switching devices.
The SCRs must be triggered by a separate power source. If the SCRs are triggered by the voltage across the SCRs, then there will be a reasonable voltage across the SCRs before the gate current will be high enough to turn them ON and at switch on, there will be a high current to charge the capacitors. This will occur at every voltage zero crossing (twice per cycle).

Your comments about SSRs suggests that you are using standard solid state relays to switch the capacitors. If this is the case, you will have high switching currents and the semiconductors will fail unless the SSR is well oversized.

Best regards,
Mark.

#5 deep

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Posted 05 February 2010 - 02:11 PM

Yes I am using standard SSRs with inbuilt zero crossing detectors.Also another external zero crossing detector gives me a upper hand in switching and at the same time i am monitaring static voltage on capacitor so that SSR will turn on at near zero potential and therefor I am not getting any current spike while switching on the capacitor.Due care is taken in SSR derating (KVAR*1.4*1.5 times).
In my current test voltage harmonics are not much (5th major with 1.6%),so how can capacitor give current harmonics of 5% to 6%?
I have observed voltage rise across SSRs on each current zero cross.(60V-80V for 50uS approx)
SSR tries to Off as cap.current go below holding current of SCR,but at same time current waveform is smooth and does not indicate that SCR went through an On-off cycle.Why?I think cap.current should show some dip at that point.(This is after current ZCD so when I found voltage rise across SSR terminal,current have already crossed its zero point).
One technical help please -How to simulate harmonic waveform?
i tried with MS Excel for upto 15th harmonics but after feeding FLUKE harmonic data, waveform doesnt look exactly the same.This may be due to other higher harmonics, but is there any other way to do that?
Actually I want to design an harmonics generater usind inverter.Is it practicle? Just a thought.

Regards,
Deep

#6 marke

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Posted 07 February 2010 - 08:24 AM

Hello deep

Solid State Relays use the voltage across the output to trigger the internal triacs. This means that the voltage must rise above zero in order to provide the trigger current. You will find that the triggering will occur at a reasonable voltage, perhaps 20 volts across the SSR.
This will result in a transient charging current with a high di/dt at each voltage zero crossing. This will put a high stress on the triac in the SSR.
If you want to use a solid state switch to switch the capacitors, it is important to switch at zero volts across the switch, not a few degrees after. This requires an external trigger source for the gate circuitry. The higher the voltage is across the switch when it closes, the higher the di/dt and current transient. I would not use a solid state relay.

QUOTE
In my current test voltage harmonics are not much (5th major with 1.6%), so how can capacitor give current harmonics of 5% to 6%?

If you have a 5th harmonic at 1.6%, you will have a harmonic current or 1.6% into a resistive load.
The impedance of a capacitor reduces with frequency, so the harmonic current into a pure capacitor will be 5 times higher at the fifth harmonic. So at the 5th harmonic, I would expect to see around 8% current.

QUOTE
I have observed voltage rise across SSRs on each current zero cross.(60V-80V for 50uS approx)
SSR tries to Off as cap.current go below holding current of SCR,but at same time current waveform is smooth and does not indicate that SCR went through an On-off cycle.Why?

It appears that the bandwidth of your current measurement methods are too low. You will definitely see the off time in the current.
The off time and the current transient are being masked by your measurements.

Best regards,
Mark.

#7 deep

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Posted 08 February 2010 - 07:09 AM

Dear Mark,
I am looking voltage & current at Tektronics DSO 100MHz.I can see voltage surge but not current.Is it possible due to CT of oscilloscope?
And regarding SSR switching ,I am using the SSR with four terminals
Terminal 1 => To Phase through Fuse or MCB
Terminal 2 => To Capacitor
Terminal 3 => Anode of opto isolation
Terminal 4 => Cathode of opto isolation

I have serched & found that SSR uses back to back SCRs and for gate drive it uses MOC3083 or alike devices so that SSR will turn on @ voltage ZCD.I used to demonstrate cap.switching at V-ZCD without any cap.current spike to the customers.
I think on existing SSR I cant control gate triggering as it is inside SSR and I have only control on Anode or cathode of optoisolator.
Is there any good link/material available for cap.switching using thyristors?I googled but most public uses contactors or thyristors in 2 phases.I am using thyristor in 3 phases.
""I would not use a solid state relay."" ????
Is it not good to use solid state switching than contactors? so that current spikes,excess derating and faster reswicthing of capacitor banks and other benefits of Solid state switching to loose


Regards,
Deep

#8 marke

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Posted 08 February 2010 - 10:02 AM

Hello Deep

By using a SSR, there must be a minimum voltage across the output before current can flow.
The SCRs typically require around 3 volts gate voltage, plus the voltage across the MOC3083 before it will switch ON.Thiscould be in the order of 3 - 5 volts.
It is comon to have a current limiting resistor in series with the gate, so there is additional voltage drop.
Once the SSR is triggered ON, provided that the current does not fall below the holding current, the voltage across the SSR will be in the order of 1 - 1.5 volts.

If the SSR turns on at say 6 volts, the current into the capacitor is limited by the impedance of the supply.
If there are no other capacitors turned on close by, then the supply will be inductive and the current will rise relatively slowly.
If there are other capacitors connected close by, then the supply will be capacitive and the peak current will be limited by the resistance of the path between the capacitor you are switching and the other capacitors on the supply. This can result in very high impulse currents with a very high di/dt and this can damage the switching elements.

If you use reverse parallel SCRs with a separate DC supply for each gate circuit that is able to be rapidly switched, you can switch with the voltage across the SCR limited to around 1 volt. This will eliminate switching transients.
This is what is normally done.

SSRs are fine for resistive and in some cases, inductive loads, but I would not use them for capacitive loads.

Best regards,
Mark.




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